When inspection variability stacks up, even a well‑profiled oven can idle. AOI reinspection loops, SPI stability, and reflow pitch decisions all show up as queues on your conveyors. Here’s a practical, queueing‑aware approach to PCB conveyor capacity planning that turns your measured cycle‑time variance into the right mix of buffer slots and parallel inspection—anchored by a parameterized automotive ECU example.
By [Name], SMT Process Engineer (S&M Co.Ltd — SMT Equipment & Conveyor Systems Engineering Team)
Disclosure: This article shares engineering methods and sizing heuristics. Validate assumptions with your own MES/PLC logs and thermal profiles before committing to CapEx or layout changes.
Key takeaways
Treat buffers as protection time against variability, not as band‑aids for undersized capacity. Use Little’s Law and M/G/1 mean‑value formulas to translate variability into slot counts.
Never size to average alone. Once stage utilization (ρ) passes ~0.80, expected queues grow sharply; add parallel AOI/SPI before simply extending buffers.
Convert reflow conveyor speed to a target line rate using effective pitch (board length plus process spacing). Then back‑calculate the pre‑reflow buffer needed to prevent starvation.
Include reinspection/rework loops in effective AOI service time; even modest false‑call fractions can require an extra AOI lane or a bypass path.
For the 160×120 mm ECU case: a high‑throughput plan typically needs 2× SPI, 3× AOI, and ~10 slots before reflow to protect a 5.7–6.0 boards/min target—tune with your measured CV and false‑call rate.
Where bottlenecks form in an SMT line
Variability accumulates where service times are longest and most uncertain. In a typical flow—SPI → placement → AOI → reflow—common queues appear:
Post‑SPI: short lane buffers to absorb printer cycles and transfer jitter.
Post‑AOI: accumulation before reflow to cover manual review/reinspection loops.
Rework path: NG diverter to touch‑up and re‑AOI; if it shares the main path, it can intermittently block flow.
Think of your line as a set of servers (machines) connected by finite queues (conveyors and buffers). The goal isn’t zero WIP; it’s enough protection time to keep reflow fed at the target rate while respecting WIP and footprint limits.
For a concise framework on translating buffer length to capacity and synchronization practice, see the S&M guide on PCB conveyor system design and synchronization in the article on speed alignment: the concepts in the public primer on PCB conveyor system design and buffer sizing pair well with this variability‑first method, and practical notes in speed and synchronization for PCB conveyors help you verify flow stability on the floor.
Measure what matters before sizing buffers
You’ll get the best results if you size from your own distributions, not catalog averages. Run at least a 4–8 hour pilot (≥500 boards per product family) and extract from MES/PLC logs:
Timestamps: start/complete at SPI and AOI, transfer events, rework loop times.
Outcomes: OK/NG with category; flag false calls later cleared as OK.
Reinspection routing: probability of re‑AOI after touch‑up and its average added time.
From the logs compute means, variances, and coefficients of variation (CV) for service times and inter‑departures. You’ll also need an empirical false‑reject fraction and a reinspection/touch‑up loop time distribution. If you need a refresher on Little’s Law in manufacturing practice, the Project Production Institute’s overview is a clear, practitioner‑oriented reference in Little’s Law, a practical approach.
The math you need for PCB conveyor capacity planning
Symbols and units (quick reference)
Symbol | Meaning | Typical unit |
|---|---|---|
λ | Throughput (arrival/departure rate) | boards/s (or boards/min) |
E[S] | Mean service time at a stage | s/board |
Var(S) | Service-time variance | s² |
CV, c_s | Coefficient of variation of service time (std/mean) | — |
c_s² | Squared coefficient of variation | — |
ρ | Utilization (λ·E[S] per lane) | — |
Wq | Mean waiting time in queue | s |
W | Mean time in system (Wq + E[S]) | s |
Lq | Mean queue length (λ·Wq) | boards |
L | Mean WIP at the stage (λ·W) | boards |
v | Conveyor speed (reflow) | m/min |
Lb | Board length in the travel direction | m |
f | Pitch load factor (accounts for added spacing) | — |
Leff | Effective pitch length per board (Lb/f) | m/board |
You don’t need a full course in queueing theory—mean‑value formulas get you far.
Little’s Law: WIP = λ × W, where λ is line throughput (boards/s) and W is average flow time (s).
Reflow rate from conveyor speed: boards/min ≈ (speed m/min × 60 ÷ effective pitch m), where effective pitch is board length divided by a load factor that reflects any added spacing (e.g., load factor 0.85 means 15% spacing). A short application note shows this conversion in context in the Texcel reflow guide PDF. Even if a reflow family spec lists “0 spacing” capability (e.g., Heller information indicates minimal spacing can be achieved on some models as shown on the Heller MK5 product info page), process stability usually benefits from 10–25% extra pitch.
M/M/1 baseline to M/G/1 mean‑value tweak: With arrival rate λ, mean service time E[S], and squared coefficient of variation c_s², utilization is ρ = λ·E[S]. A common mean‑value approximation for queue delay is Wq ≈ (ρ·E[S]·(1 + c_s²)) / (2·(1 − ρ)). Total time is W = Wq + E[S]. See an accessible summary in the Pollaczek–Khinchine formula overview.
Effective AOI service time with reinspection: If a fraction pR of boards incur an average extra ΔS (touch‑up + re‑AOI + transfers), then E[S]_eff ≈ E[S] + pRΔS, and variance increases accordingly. Recalculate ρ and Wq with the updated first and second moments.
Here’s the deal: once ρ creeps above ~0.80 at an inspection stage, Wq grows non‑linearly. Buffers can only mask that for a short while; capacity (parallelization) is the durable fix.
Worked example for an automotive ECU line
The inputs below reflect a common automotive ECU scenario. Replace assumptions (CVs, reinspection fraction, spacing) with your measured values.
Inputs and assumptions
Board: 160 × 120 mm; panelization 2 × 1.
SPI: mean service E[S_SPI] = 12 s; assume CV_SPI ≈ 0.3 (stable printer).
AOI: mean service E[S_AOI] = 18 s; assume CV_AOI ≈ 0.5.
Reinspection/rework at AOI: pR = 8% combined (false calls + true defects); average added loop time ΔS_loop = 40 s.
Reflow: 9 zones; conveyor speed v = 1.2 m/min; assume effective pitch load factor f = 0.85 (≈15% spacing). Use the longer board dimension in flow: Lb = 0.16 m.
KPI priority: maximize throughput/OTD subject to WIP ≤ 20 boards between SPI → AOI → pre‑reflow buffer.
Reflow’s implied line rate
Effective length per board Leff = Lb / f = 0.16 / 0.85 ≈ 0.188 m/board.
Boards/min at reflow BR = v / Leff = 1.2 / 0.188 ≈ 6.37 boards/min → ≈ 382 bph.
Treat this as an upper bound conditional on thermal profile.
SPI capacity and need for parallelization
Single SPI capacity μ_SPI = 1/12 s ≈ 5.0 boards/min. Any target above 5.0 boards/min makes ρ ≥ 1 (unstable). To pursue ~6 boards/min, add a second SPI.
With two SPIs and perfect load split, λ_target = 6.0/min → λ_each = 3.0/min = 0.05/s; ρ_each = λ_each×E[S] = 0.05×12 = 0.60.
Using M/G/1 mean‑value with c_s^2 = 0.09: Wq ≈ [0.60×12×1.09]/[2×0.40] ≈ 9.8 s; W ≈ 21.8 s; L_each ≈ λ_each×W ≈ 0.05×21.8 ≈ 1.09 boards. Across both lanes, SPI stage WIP ≈ 2.2 boards.
AOI effective demand with reinspection
Effective mean: E[S]_eff ≈ 18 + 0.08×40 = 21.2 s.
Conservative variance uplift: if base CV≈0.5, Var_base=(0.5×18)^2=81 s²; add loop term pRΔS²≈0.08×1600=128 s² → Var_eff≈209 s² → c_s^2≈209/(21.2)^2≈0.465.
Single AOI capacity μ≈1/21.2 s≈2.83/min. To feed 6.0/min, parallelization is required. With two AOIs: λ_each=3.0/min=0.05/s→ ρ≈1.06 (not feasible). With three AOIs: λ_each=2.0/min=0.0333/s→ ρ≈0.71.
Wq_each ≈ [0.71×21.2×(1+0.465)]/[2×0.29] ≈ 38 s; W≈59 s. L_each≈λ_each×W≈0.0333×59≈1.97 boards → AOI stage WIP across 3 lanes ≈ 5.9 boards.
Pre‑reflow accumulation buffer sizing
Intent: protect reflow from AOI variability and manual reviews.
Protection time T_protect should at least cover a representative AOI queue delay. Choose 75 s for a high‑throughput target.
At λ = 6.0/min = 0.10/s: expected slots ≈ λ×T_protect ≈ 0.10×75 = 7.5 → round to 8.
Add 20–40% safety for transfer jitter and diverter actions → 10–12 slots. Use your floor constraints to pick 10 or 12.
WIP constraint check (≤ 20 boards between SPI→AOI→pre‑reflow)
SPI ≈ 2.2; AOI ≈ 5.9; pre‑reflow buffer 10–12; transfers 1–2.
Sum at 10 slots: 2.2 + 5.9 + 10 + 1.0–2.0 ≈ 19.1–20.1. If you must stay under 20, start with 10 slots and trim AOI variability (better recipes, review routing) or run slightly lower at 5.7–5.8 boards/min until AOI tuning lowers pR.
Micro product example (neutral) If your calculation calls for ~10 slots before reflow and your board is 160 mm long, a compact inspection/accumulation conveyor with adjustable width and segment‑level control is a practical choice. For instance, the public spec of the inspection conveyor product lists configurable lengths that can be combined to achieve the 10–12 slot requirement at your effective pitch; match module length to slot count using Leff and confirm speed synchronization with your PLC. This is an illustrative mapping—validate final dimensions and controls against your process window.
Sensitivity notes you should test on your floor
Lowering AOI pR from 8% to 5% cuts E[S]_eff by 1.2 s and meaningfully reduces Wq; you may avoid a third AOI at modest line rates.
If profiling forces reflow pitch to f = 0.75 (25% spacing), BR drops to ≈5.63/min; your bottleneck may shift and the buffer can be shortened accordingly.
For a short, accessible summary of why expected queues rise with both utilization and variance, the Pollaczek–Khinchine overview is a useful companion reference.
Decision matrix for buffers versus parallel inspection
The table below maps common situations to actions with the primary KPI here—throughput/OTD—front and center.
Situation | Primary KPI impact | Preferred action | Rationale |
|---|---|---|---|
AOI ρ ≥ 0.80 and rising Wq; false‑calls >5% | Throughput at risk | Add AOI lane; tune recipes | Capacity neutralizes non‑linear queue growth; recipe tuning lowers E[S]_eff |
SPI ρ ≥ 0.80 but AOI stable | Throughput at risk | Add SPI lane | Printers cap rate; buffers can’t fix unstable ρ |
Short AOI micro‑stops starve reflow | OTD slips from idling | Add 60–90 s pre‑reflow buffer | Converts bursts into steady feed via T_protect |
Rework loop blocks mainline | Local blocking; WIP spikes | Add NG diverter and short dedicated rework buffer | Decouples rework from main conveyor |
High‑mix changeovers | Both throughput and WIP | Use bypass/dual‑track with smart scheduling | Keeps hot product flowing while staging next job |
Spreadsheet steps and a tiny algorithm to reuse
You can implement the method in a simple worksheet and reuse it across products.
Cell formulas (units in seconds unless noted)
Reflow pitch: Leff = Lb / f
Reflow rate: BR (boards/min) = v / Leff
Effective AOI mean: ESe = ES + pR×ΔS
Effective AOI variance (conservative): Var_e ≈ Var_base + pR×(ΔS)^2
AOI squared CV: c_s^2 = Var_e / (ESe)^2
Utilization per lane: ρ = (λ / nlanes) × ESe
Queue delay per lane: Wq ≈ [ρ×ESe×(1 + c_s^2)] / [2×(1 − ρ)]
Pre‑reflow slots: Slots ≈ λ×T_protect × (1 + safety_margin)
Pseudo‑algorithm
Given target λ, board length Lb, spacing factor f, SPI and AOI service stats, and WIP cap:
1) Compute Leff = Lb / f and BR = v / Leff.
2) Set λ_target = min(BR, business target). If λ_target > SPI capacity, set n_SPI so ρ_SPI ≤ 0.75.
3) Build AOI effective service stats with pR and ΔS; choose n_AOI so ρ_AOI ≤ 0.75–0.80.
4) Pick T_protect (60–90 s typical) and compute pre‑reflow Slots = ceil(λ_target×T_protect×(1+safety)).
5) Sum WIP across SPI, AOI, transfers, and buffer; if > cap, iterate: reduce pR via recipe, tweak λ, or adjust Slots.
6) Validate on the floor; log Wq and starvation frequency; update parameters.
Checklist to validate on the floor
Run a ≥4‑hour pilot on the target product family; collect ≥500 boards with start/stop timestamps at SPI/AOI and rework loop events.
Compute E[S], Var(S), CV for SPI and AOI; estimate pR and average ΔS from logs.
Confirm effective reflow pitch (tachometer + profile) and absence of starvation/blocking in the logs.
Size n_SPI and n_AOI so ρ ≤ 0.80; then set pre‑reflow buffer to 60–90 s protection with a 20–40% safety margin.
Re‑measure after recipe tuning and adjust Slots and nlanes if pR or CV changes.
Next steps and further reading
If you want a deeper dive into slot‑length mapping and module selection, the public primer on PCB conveyor system design and buffer sizing is a good companion to this method. For AOI programming practices that aim to cut false calls, vendor thought‑leadership like Koh Young’s note on AI‑assisted AOI and yield improvements offers context; validate results with your own logs. If you need neutral help translating your calculated slot counts into specific module lengths and controls, S&M can provide conveyor specifications and integration guidance.
SEO note for implementers: this queueing‑first approach to PCB conveyor capacity planning is most reliable when grounded in your measured distributions; avoid copying catalog UPH without variance and reinspection data.