{"id":4185,"date":"2026-03-06T03:30:38","date_gmt":"2026-03-05T19:30:38","guid":{"rendered":"https:\/\/www.chuxin-smt.com\/?p=4185"},"modified":"2026-03-06T03:30:38","modified_gmt":"2026-03-05T19:30:38","slug":"pcb-conveyor-system-design-ultimate-guide","status":"publish","type":"post","link":"https:\/\/www.chuxin-smt.com\/es\/pcb-conveyor-system-design-ultimate-guide\/","title":{"rendered":"PCB Conveyor System Design: Optimize Dual\u2011Lane SMT Layout for Maximum Throughput"},"content":{"rendered":"<figure class=\"wp-block-image aligncenter size-large\"><img fetchpriority=\"high\" decoding=\"async\" width=\"1536\" height=\"1024\" src=\"https:\/\/www.chuxin-smt.com\/wp-content\/uploads\/2026\/03\/1772682500-image_1772680407-cw583h7p.jpeg\" alt=\"Engineering infographic of a dual-lane SMT line with buffers, NG\/OK diverter, and Hermes\/CFX data flows\" class=\"wp-image-4183\" srcset=\"https:\/\/www.chuxin-smt.com\/wp-content\/uploads\/2026\/03\/1772682500-image_1772680407-cw583h7p.jpeg 1536w, https:\/\/www.chuxin-smt.com\/wp-content\/uploads\/2026\/03\/1772682500-image_1772680407-cw583h7p-300x200.jpeg 300w, https:\/\/www.chuxin-smt.com\/wp-content\/uploads\/2026\/03\/1772682500-image_1772680407-cw583h7p-1024x683.jpeg 1024w, https:\/\/www.chuxin-smt.com\/wp-content\/uploads\/2026\/03\/1772682500-image_1772680407-cw583h7p-768x512.jpeg 768w, https:\/\/www.chuxin-smt.com\/wp-content\/uploads\/2026\/03\/1772682500-image_1772680407-cw583h7p-18x12.jpeg 18w\" sizes=\"(max-width: 1536px) 100vw, 1536px\" title=\"PCB Conveyor System Design: Optimize Dual\u2011Lane SMT Layout for Maximum Throughput - S&amp;M Co.Ltd\" \/><\/figure>\n\n\n\n<p>High\u2011speed consumer electronics lines live or die on conveyor decisions. On dual\u2011lane SMT layouts, a few millimeters of pitch or seconds of accumulation can be the difference between hitting UPH and babysitting blockages. This ultimate guide shows exactly how to back\u2011calculate your PCB conveyor system design from target capacity, size buffers with Little\u2019s Law, position NG\/OK diverters, and wire in IPC\u2011HERMES\u20119852 plus IPC\u20112591 (CFX) for reliable routing and traceability\u2014while keeping SMEMA as a safe fallback. We\u2019ll work through a complete numeric example you can adapt to your factory.<\/p>\n\n\n\n<hr class=\"wp-block-separator\" \/>\n\n\n\n<h2 class=\"wp-block-heading\">Principales conclusiones<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Start with demand, not hardware: takt per lane (s\/board) = 3600 \u00f7 UPH_lane; UPH_lane = UPH_total \u00f7 lanes.<\/p><\/li><li><p>Use Little\u2019s Law to size buffers: WIP (boards) = arrival rate \u03bb (boards\/s) \u00d7 waiting time W (s); add 20\u201340% safety for variability\/MTBA.<\/p><\/li><li><p>Place accumulation where it prevents starvation\/blocking: post\u2011loader, printer\u2192placer, placer\u2192reflow, and pre\u2011AOI.<\/p><\/li><li><p>Hermes handles horizontal board handover with IDs\/metadata; CFX carries factory\u2011level events\/traceability; SMEMA remains a fallback. See the official IPC\u2011HERMES\u20119852 v1.6 PDF by The Hermes Standard organization for message flows and lane\u2011aware fields.<\/p><\/li><li><p>NG\/OK routing steals time only when it fires; model its delay as a fractional loss tied to NG% and actuation timing.<\/p><\/li><li><p>For dual\u2011lane lines, synchronize splitter\/merger logic and auto\u2011width control to lane takt to avoid micro\u2011stoppages.<\/p><\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator\" \/>\n\n\n\n<h2 class=\"wp-block-heading\">What \u201cgood\u201d looks like on a dual\u2011lane high\u2011speed SMT line<\/h2>\n\n\n\n<p>On mature dual\u2011lane consumer lines, planners target tight, predictable flow rather than peak speed alone. Hallmark outcomes include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Stable UPH within \u00b12\u20133% of plan over a full shift, with Overall Equipment Effectiveness (OEE) &gt; 80% and First Pass Yield (FPY) &gt; 98%.<\/p><\/li><li><p>No chronic starvation at placement and no reflow\u2011side blocking; visible WIP limits with buffers sized to protect takt, not to hide problems.<\/p><\/li><li><p>Deterministic routing: board IDs and product types are known before each handover; lane merges don\u2019t thrash; NG\/OK decisions are executed without ambiguous states.<\/p><\/li><li><p>Changeovers fit into planned windows; width adjustment and recipe selection complete before the next board arrives.<\/p><\/li>\n<\/ul>\n\n\n\n<p>Why does conveyor design dominate these outcomes? Because conveyors and buffers set the cadence between bottleneck machines. A design that respects takt and variability will let your fastest assets actually run; a design that guesses on pitch and accumulation will convert micro\u2011delays into line\u2011wide losses. Put plainly, disciplined PCB conveyor system design is a force multiplier for UPH and OEE.<\/p>\n\n\n\n<hr class=\"wp-block-separator\" \/>\n\n\n\n<h2 class=\"wp-block-heading\">Standards that make routing and traceability work<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>IPC\u2011HERMES\u20119852 v1.6. The Hermes standard replaces legacy electrical handshakes with a TCP\/IP protocol that carries board metadata, including unique identifiers and lane\u2011aware connections. The v1.6 document formalizes fields such as LaneId and introduces supervisory services for routing and recipe selection. See the official specification in the IPC\u2011HERMES\u20119852 v1.6 PDF by The Hermes Standard organization for scope and message sequences: consult the figures describing ServiceDescription, BoardForecast, and MachineReady exchanges in 2024\u2019s version 1.6.<\/p><ul><li><p>Reference: The Hermes Standard, IPC\u2011HERMES\u20119852 Version 1.6 (July 2024). Read the official PDF via the Hermes site: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.the-hermes-standard.info\/wp-content\/uploads\/IPC-HERMES-9852-Version-1.6-HERMES-SITE.pdf\">https:\/\/www.the-hermes-standard.info\/wp-content\/uploads\/IPC-HERMES-9852-Version-1.6-HERMES-SITE.pdf<\/a><\/p><\/li><\/ul><\/li><li><p>IPC\u20112591 CFX. CFX provides factory\u2011wide, plug\u2011and\u2011play data exchange for real\u2011time KPIs, material\/board genealogy, and quality results. It complements Hermes\u2019 horizontal transport by enabling vertical context in MES\/analytics and can inform routing based on AOI\/X\u2011ray outcomes.<\/p><ul><li><p>Reference: IPC\u2019s overview of Connected Factory Exchange explains roles and complementarity: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.ipc.org\/about-cfx-global-standard-smart-manufacturing-enablement\">https:\/\/www.ipc.org\/about-cfx-global-standard-smart-manufacturing-enablement<\/a><\/p><\/li><\/ul><\/li><li><p>SMEMA (IPC\u2011SMEMA\u20119851). SMEMA defines the electrical handshake for board transfer (presence\/ready\/stop). It carries no board metadata. Keep SMEMA enabled as a fallback for legacy compatibility and fail\u2011safe transport even when Hermes\/CFX are deployed.<\/p><ul><li><p>Reference: IPC standard overview pages describe SMEMA\u2019s scope and the context for Hermes as its successor.<\/p><\/li><\/ul><\/li>\n<\/ul>\n\n\n\n<p>How they fit together in practice<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Hermes moves boards with IDs and product type between adjacent modules and routers\/diverters (horizontal).<\/p><\/li><li><p>CFX streams events and quality outcomes to MES (vertical). MES decides NG\/OK routing and release strategies; Hermes carries the per\u2011board route tags to the next node.<\/p><\/li><li><p>SMEMA remains wired so transport is safe even if IP links go down.<\/p><\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator\" \/>\n\n\n\n<h2 class=\"wp-block-heading\">Methods and formulas you\u2019ll use<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Split target throughput by lanes<\/p><ul><li><p>UPH_lane = UPH_total \u00f7 lanes<\/p><\/li><li><p>Takt (s\/board) = 3600 \u00f7 UPH_lane<\/p><\/li><\/ul><\/li><li><p>Yield\u2011adjusted effective throughput<\/p><ul><li><p>Effective_UPH = Raw_UPH \u00d7 (1 \u2212 NG%) \u00d7 (1 \u2212 Diverter_Delay_Factor)<\/p><\/li><li><p>Approximate Diverter_Delay_Factor = NG% \u00d7 (t_divert \u00f7 takt)<\/p><\/li><\/ul><\/li><li><p>Little\u2019s Law for buffer sizing<\/p><ul><li><p>WIP (boards) = \u03bb \u00d7 W, where \u03bb = UPH_lane \u00f7 3600 (boards\/s) and W is the protection time you want (s). Add 20\u201340% safety WIP depending on variability (MTBA\/MTTR).<\/p><\/li><\/ul><\/li><li><p>Conveyor pitch and speed sanity checks<\/p><ul><li><p>Pitch \u2248 PCB length + gap (typ. 20\u201380 mm depending on sensor spacing and stop accuracy)<\/p><\/li><li><p>Speed (m\/min) \u2248 Pitch (m) \u00d7 (UPH_lane \u00f7 60), kept within module specs<\/p><\/li><\/ul><\/li>\n<\/ul>\n\n\n\n<p>These methods are the backbone of practical PCB conveyor system design\u2014consistent math that keeps mechanics and controls aligned with demand.<\/p>\n\n\n\n<hr class=\"wp-block-separator\" \/>\n\n\n\n<h2 class=\"wp-block-heading\">PCB conveyor system design, step by step \u2014 worked dual\u2011lane example<\/h2>\n\n\n\n<p>Scenario<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Product: Smartphone mainboard, single PCB (no panel), 150 \u00d7 80 mm, 0.8 mm thick, 0.15 kg<\/p><\/li><li><p>Line: Dual\u2011lane from printer through placement; lanes merge before reflow; post\u2011reflow AOI with NG\/OK diverter and NG loop\u2011back buffer<\/p><\/li><li><p>Target capacity: UPH_total = 1,200 boards\/hour<\/p><\/li><li><p>NG rate at AOI: 2% (sent to repair loop); diverter actuation and decision overhead per NG event: 0.8 s (typical vendor range; validate against the chosen diverter\u2019s datasheet)<\/p><\/li><li><p>Available straight length between modules: 1,000\u20131,400 mm segments<\/p><\/li><li><p>Interfaces: IPC\u2011HERMES\u20119852 + IPC\u20112591 CFX, SMEMA fallback<\/p><\/li>\n<\/ul>\n\n\n\n<ol class=\"wp-block-list\">\n<li><p>Takt by lane<\/p><\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>UPH_lane = 1,200 \u00f7 2 = 600 boards\/hour<\/p><\/li><li><p>Takt = 3600 \u00f7 600 = 6.0 s\/board\/lane<\/p><\/li>\n<\/ul>\n\n\n\n<ol class=\"wp-block-list\" start=\"2\">\n<li><p>Choose pitch and compute conveyor speed<\/p><\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Nominal pitch = PCB length + gap = 150 mm + 30 mm = 180 mm = 0.18 m<\/p><\/li><li><p>Speed needed (per lane) \u2248 0.18 \u00d7 (600 \u00f7 60) = 0.18 \u00d7 10 = 1.8 m\/min<\/p><\/li><li><p>Sanity: This sits well within common conveyor ranges. For example, an inspection conveyor with 0.5\u201320 m\/min speed capability provides headroom; see the S&amp;M Inspection Conveyor specifications for an example of this speed window: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.chuxin-smt.com\/es\/products\/conveyor-inspection-conveyor\/\">https:\/\/www.chuxin-smt.com\/products\/conveyor-inspection-conveyor\/<\/a><\/p><\/li>\n<\/ul>\n\n\n\n<ol class=\"wp-block-list\" start=\"3\">\n<li><p>Size buffers using Little\u2019s Law<\/p><\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Arrival rate \u03bb = 600 \u00f7 3600 = 0.1667 boards\/s per lane<\/p><\/li>\n<\/ul>\n\n\n\n<p>Protection objectives and W targets<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Printer\u2192Placer starvation protection: W = 30 s \u2192 WIP = 0.1667 \u00d7 30 = 5.0 boards \u2192 add 30% safety \u21d2 6.5 \u2248 7 slots per lane<\/p><\/li><li><p>Placer\u2192Reflow blocking protection: W = 90 s \u2192 WIP = 0.1667 \u00d7 90 = 15.0 \u2192 +30% \u21d2 19.5 \u2248 20 slots per lane<\/p><\/li><li><p>Pre\u2011AOI surge absorption: W = 45 s \u2192 WIP = 0.1667 \u00d7 45 = 7.5 \u2192 +30% \u21d2 9.75 \u2248 10 slots per lane<\/p><\/li>\n<\/ul>\n\n\n\n<ol class=\"wp-block-list\" start=\"4\">\n<li><p>Account for NG\/OK routing penalty<\/p><\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Diverter_Delay_Factor \u2248 NG% \u00d7 (t_divert \u00f7 takt) = 0.02 \u00d7 (0.8 \u00f7 6.0) = 0.0027 (\u2248 0.27%)<\/p><\/li><li><p>Effective_UPH \u2248 1,200 \u00d7 (1 \u2212 0.02) \u00d7 (1 \u2212 0.0027) \u2248 1,200 \u00d7 0.98 \u00d7 0.9973 \u2248 1,173 UPH<\/p><\/li><li><p>Implication: With 2% NG and 0.8 s\/event, the routing penalty is small; don\u2019t oversize for this alone\u2014focus on variability and repair loop capacity.<\/p><\/li>\n<\/ul>\n\n\n\n<ol class=\"wp-block-list\" start=\"5\">\n<li><p>Check physical lengths<\/p><\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>A 7\u2011slot inline accumulator with 180 mm pitch needs \u2248 1,260 mm of effective length (7 \u00d7 180 mm), within the 1,000\u20131,400 mm windows if you use compact buffering (e.g., a short conveyor plus a shuttle or magazine buffer where space is tight).<\/p><\/li><li><p>For 20\u2011slot protection before reflow, inline length alone would be \u2248 3.6 m per lane; that\u2019s footprint\u2011heavy. Use a compact accumulator (e.g., vertical buffer or shuttle) sized for 20 boards per lane, or relocate some accumulation pre\u2011merger where you have space.<\/p><\/li>\n<\/ul>\n\n\n\n<p>Table 1. Inputs and core results (worked example)<\/p>\n\n\n\n<figure class=\"wp-block-table\">\n<table class=\"has-fixed-layout\">\n<colgroup><col \/><col \/><\/colgroup><tbody><tr><th colspan=\"1\" rowspan=\"1\"><p>Item<\/p><\/th><th colspan=\"1\" rowspan=\"1\"><p>Value<\/p><\/th><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>UPH_total<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>1,200 boards\/h<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Lanes<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>2<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>UPH_lane<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>600 boards\/h<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Takt per lane<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>6.0 s\/board<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Tama\u00f1o PCB<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>150 \u00d7 80 \u00d7 0.8 mm<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Pitch<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>180 mm<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Conveyor speed target<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>1.8 m\/min<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>NG rate<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>2%<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Diverter time (per NG)<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>0.8 s<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Effective UPH<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>\u2248 1,173 boards\/h<\/p><\/td><\/tr><\/tbody>\n<\/table>\n<\/figure>\n\n\n\n<p>Table 2. Buffer sizing by objective (Little\u2019s Law +30% safety)<\/p>\n\n\n\n<figure class=\"wp-block-table\">\n<table class=\"has-fixed-layout\">\n<colgroup><col \/><col \/><col \/><col \/><\/colgroup><tbody><tr><th colspan=\"1\" rowspan=\"1\"><p>Location<\/p><\/th><th colspan=\"1\" rowspan=\"1\"><p>W target (s)<\/p><\/th><th colspan=\"1\" rowspan=\"1\"><p>WIP calc (boards)<\/p><\/th><th colspan=\"1\" rowspan=\"1\"><p>Rounded capacity per lane<\/p><\/th><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Printer\u2192Placer<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>30<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>5.0<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>7<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Placer\u2192Reflow<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>90<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>15.0<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>20<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Pre\u2011AOI<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>45<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>7.5<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>10<\/p><\/td><\/tr><\/tbody>\n<\/table>\n<\/figure>\n\n\n\n<p>Design notes<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>If floor space is constrained before reflow, consider a shuttle or magazine buffer. A single\u2011station shuttle can decouple lanes and create compact accumulation; review a single\u2011station shuttle module\u2019s footprint and compatibility to slot between placer and oven. For a reference design, see a single\u2011station shuttle conveyor example: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.chuxin-smt.com\/es\/products\/single-station-shuttle-conveyor\/\">https:\/\/www.chuxin-smt.com\/products\/single-station-shuttle-conveyor\/<\/a><\/p><\/li><li><p>Keep pitch consistent across accumulators and link conveyors so sensors and stop units don\u2019t create micro\u2011oscillation at merges. This is a subtle but critical aspect of PCB conveyor system design that preserves lane takt.<\/p><\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator\" \/>\n\n\n\n<h2 class=\"wp-block-heading\">NG\/OK diverters and accumulators: placement, sizing, and timing sensitivity<\/h2>\n\n\n\n<p>Colocaci\u00f3n<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>After reflow AOI, install an NG\/OK diverter with a clearly defined NG buffer (repair loop or magazine) and an OK merge back to the unloader. Keep any flip or orientation change off the takt\u2011critical path unless the product requires it.<\/p><\/li>\n<\/ul>\n\n\n\n<p>Sizing the NG buffer<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Expected NG arrival rate \u03bb_NG = (UPH_total \u00d7 NG%) \u00f7 3600. In our example, \u03bb_NG = (1,200 \u00d7 0.02) \u00f7 3600 \u2248 0.0067 boards\/s (\u2248 24.0 boards\/h).<\/p><\/li><li><p>If the repair station takt is 90 s\/board and releases back to AOI or a verification gate, then WIP needed to avoid NG\u2011side blocking for W = 300 s surge is L = \u03bb_NG \u00d7 W \u2248 0.0067 \u00d7 300 \u2248 2.0 boards. Add 40% safety for repair variability \u21d2 \u2248 3 boards of immediate buffer, plus magazine\/loop capacity sized for sustained peaks.<\/p><\/li>\n<\/ul>\n\n\n\n<p>Timing sensitivity (illustrative bands; validate with the chosen model\u2019s datasheet)<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>UPH loss fraction \u2248 NG% \u00d7 (t_divert \u00f7 takt). With takt = 6.0 s:<\/p><ul><li><p>t_divert = 0.3 s at 2% NG \u21d2 0.10% loss<\/p><\/li><li><p>t_divert = 0.6 s at 2% NG \u21d2 0.20% loss<\/p><\/li><li><p>t_divert = 1.0 s at 5% NG \u21d2 0.83% loss<\/p><\/li><\/ul><\/li><li><p>Conclusion: Actuation speed matters, but variability and repair flow dominate. Focus on smooth merges and predictable buffer release.<\/p><\/li>\n<\/ul>\n\n\n\n<p>Accumulator choices<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Inline accumulators are simple but footprint\u2011hungry for big W targets. Vertical\/multi\u2011layer buffers compress footprint at the cost of extra mechanics; size by slots, not time alone. For cooling or dwell requirements, pair accumulation with controlled cooling surfaces; see a practical overview of PCB cooling conveyors for considerations like dwell time and heat removal: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.chuxin-smt.com\/es\/slug-pcb-cooling-conveyors-a-comprehensive-guide-to-smt-quality-and-efficiency\/\">https:\/\/www.chuxin-smt.com\/slug-pcb-cooling-conveyors-a-comprehensive-guide-to-smt-quality-and-efficiency\/<\/a><\/p><\/li>\n<\/ul>\n\n\n\n<p>Micro\u2011example with a neutral product reference<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>For inspection or decoupling after the printer, a small adjustable\u2011speed inspection conveyor (0.5\u201320 m\/min range) can be tuned to the 1.8 m\/min target we computed, leaving margin for recovery. An example spec window is documented on the S&amp;M Inspection Conveyor page; this is illustrative only\u2014validate against your chosen vendor and model.<\/p><\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator\" \/>\n\n\n\n<h2 class=\"wp-block-heading\">Changeover and auto\u2011width control for dual lanes<\/h2>\n\n\n\n<p>High\u2011mix isn\u2019t our primary scenario, but even consumer lines face ECOs and SKU rotations. Recipe\u2011driven auto\u2011width and early recipe selection prevent dead time.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Width metadata via Hermes. Hermes v1.6 supports conveying product type and lane\u2011aware connections so downstream modules can prepare before the next board arrives. Use BoardForecast from the upstream splitter; the downstream machine returns MachineReady with the matching ForecastId, then adjusts width before StartTransport.<\/p><\/li><li><p>Recipe binding in MES\/CFX. Map ProductTypeId to recipes at the MES. When AOI\/X\u2011ray reports an NG via CFX, the MES tags that board\u2019s route for the diverter using Hermes metadata to carry it to the actuating module.<\/p><\/li><li><p>Practical SOP: Trigger width auto\u2011adjust as soon as MachineReady is accepted; require a minimum settle time margin equal to 1.2\u00d7 your lane takt delta to the next arrival.<\/p><\/li><li><p>Further reading: For step\u2011by\u2011step considerations on conveyor width adjustment mechanisms and tolerances, see this practical guide on conveyor width control: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.chuxin-smt.com\/sl\/slug-a-comprehensive-guide-to-pcb-conveyor-width-adjustment\/\">https:\/\/www.chuxin-smt.com\/sl\/slug-a-comprehensive-guide-to-pcb-conveyor-width-adjustment\/<\/a><\/p><\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator\" \/>\n\n\n\n<h2 class=\"wp-block-heading\">RFP\/spec checklist for conveyors and diverters<\/h2>\n\n\n\n<p>Use this compact template to request quotes and compare vendors apples\u2011to\u2011apples.<\/p>\n\n\n\n<figure class=\"wp-block-table\">\n<table class=\"has-fixed-layout\">\n<colgroup><col \/><col \/><col \/><\/colgroup><tbody><tr><th colspan=\"1\" rowspan=\"1\"><p>Spec field<\/p><\/th><th colspan=\"1\" rowspan=\"1\"><p>Requirement in this example<\/p><\/th><th colspan=\"1\" rowspan=\"1\"><p>Notas<\/p><\/th><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Speed range (m\/min)<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>0.5\u201320 (target setpoint \u2248 1.8)<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Verify closed\u2011loop stability at low speeds<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Pitch control<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>180 mm nominal, \u00b11 mm stop<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Sensor spacing and stop accuracy<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>PCB size window (L\u00d7W\u00d7T)<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>\u2265 150\u00d780\u00d70.8 mm<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Check lane center reference<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Lane configuration<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Dual\u2011lane from printer to merge<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Splitter\/merger compatibility<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Accumulator capacity<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>7 \/ 20 \/ 10 slots by location per lane<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Provide slot pitch and footprint<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Diverter actuation latency<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>\u2264 0.6 s (typical target)<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Verify datasheet and duty cycle<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Interfaces<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>IPC\u2011HERMES\u20119852 + IPC\u20112591 CFX + SMEMA<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Include LAN redundancy plan<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Barcode integration<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Inline code reader mounts<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Lighting and read\u2011rate targets<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>ESD and IP rating<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>ESD\u2011safe; IP20+ shop floor<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Site\u2011specific requirements<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>PLC\/HMI<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Recipe and manual jog modes<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Maintenance lockouts<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Ancho autom\u00e1tico<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Recipe\u2011driven with Hermes metadata<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Dual\u2011lane independent control<\/p><\/td><\/tr><tr><td colspan=\"1\" rowspan=\"1\"><p>Cooling\/dwell (if needed)<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Pre\u2011reflow cooling or dwell spec<\/p><\/td><td colspan=\"1\" rowspan=\"1\"><p>Confirm thermal capacity<\/p><\/td><\/tr><\/tbody>\n<\/table>\n<\/figure>\n\n\n\n<hr class=\"wp-block-separator\" \/>\n\n\n\n<h2 class=\"wp-block-heading\">Lessons from the field: a short engineering example<\/h2>\n\n\n\n<p>A dual\u2011lane consumer line struggled to exceed 1,050 UPH against a 1,200 UPH plan. Placement never starved on paper, yet the AOI queue oscillated and the reflow entry frequently blocked. A quick study found:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Pitch varied from 170 to 200 mm across ad\u2011hoc conveyor swaps; at 600 UPH\/lane, that created 0.3\u20130.6 m\/min setpoint changes and inconsistent sensor timing.<\/p><\/li><li><p>Pre\u2011AOI accumulation was only 4 slots per lane\u2014half of the 10 slots Little\u2019s Law justified\u2014so any brief AOI pause caused upstream blocking.<\/p><\/li><li><p>The NG diverter shared a congested merge; actuation occasionally delayed OK flow.<\/p><\/li>\n<\/ul>\n\n\n\n<p>Fix<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Standardized pitch to 180 mm across segments and set speed to 1.8 m\/min with closed\u2011loop control.<\/p><\/li><li><p>Added a compact shuttle buffer sized to 10 slots per lane before AOI and relocated the NG diverter to a dedicated bypass with its own short buffer.<\/p><\/li><li><p>Enabled Hermes BoardForecast\u2192MachineReady exchanges at the merge so the downstream unloader could pre\u2011select recipes and widths.<\/p><\/li>\n<\/ul>\n\n\n\n<p>Outcome<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Effective UPH improved to 1,180\u20131,190 with OEE +6 points. FPY held at 98.3%. Operators reported fewer micro\u2011stoppages and smoother merges. The lesson: get the math right, then make the mechanics obey the math.<\/p><\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator\" \/>\n\n\n\n<h2 class=\"wp-block-heading\">Appendix<\/h2>\n\n\n\n<p>Glossary (selected)<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Takt: The cadence required to meet demand (seconds per board per lane).<\/p><\/li><li><p>UPH: Units per hour; used here as boards\/hour.<\/p><\/li><li><p>Little\u2019s Law: L = \u03bb \u00d7 W; average WIP equals arrival rate times waiting time.<\/p><\/li><li><p>Hermes: IPC\u2011HERMES\u20119852; TCP\/IP protocol for board transfer with metadata.<\/p><\/li><li><p>CFX: IPC\u20112591; factory\u2011wide data exchange standard for events, genealogy, KPIs.<\/p><\/li><li><p>SMEMA: IPC\u2011SMEMA\u20119851; electrical handshake for safe board transfer.<\/p><\/li>\n<\/ul>\n\n\n\n<p>References and further reading<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>The Hermes Standard\u2019s official IPC\u2011HERMES\u20119852 Version 1.6 PDF includes message flows and lane\u2011aware fields; see the 2024 specification: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.the-hermes-standard.info\/wp-content\/uploads\/IPC-HERMES-9852-Version-1.6-HERMES-SITE.pdf\">https:\/\/www.the-hermes-standard.info\/wp-content\/uploads\/IPC-HERMES-9852-Version-1.6-HERMES-SITE.pdf<\/a><\/p><\/li><li><p>IPC\u2019s Connected Factory Exchange overview explains CFX\u2019s role and complementarity with Hermes: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.ipc.org\/about-cfx-global-standard-smart-manufacturing-enablement\">https:\/\/www.ipc.org\/about-cfx-global-standard-smart-manufacturing-enablement<\/a><\/p><\/li><li><p>A practical explainer of Little\u2019s Law, with examples for WIP and lead time: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.isixsigma.com\/dictionary\/littles-law\/\">https:\/\/www.isixsigma.com\/dictionary\/littles-law\/<\/a><\/p><\/li>\n<\/ul>\n\n\n\n<p>Internal resources (contextual learning)<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Example inspection conveyor speed window and sizing context: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.chuxin-smt.com\/es\/products\/conveyor-inspection-conveyor\/\">https:\/\/www.chuxin-smt.com\/products\/conveyor-inspection-conveyor\/<\/a><\/p><\/li><li><p>Single\u2011station shuttle module for compact accumulation: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.chuxin-smt.com\/es\/products\/single-station-shuttle-conveyor\/\">https:\/\/www.chuxin-smt.com\/products\/single-station-shuttle-conveyor\/<\/a><\/p><\/li><li><p>Cooling\/dwell considerations for conveyors: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.chuxin-smt.com\/es\/slug-pcb-cooling-conveyors-a-comprehensive-guide-to-smt-quality-and-efficiency\/\">https:\/\/www.chuxin-smt.com\/slug-pcb-cooling-conveyors-a-comprehensive-guide-to-smt-quality-and-efficiency\/<\/a><\/p><\/li><li><p>Width adjustment mechanisms and tolerances guide: <a target=\"_blank\" rel=\"noopener noreferrer nofollow\" class=\"link\" href=\"https:\/\/www.chuxin-smt.com\/sl\/slug-a-comprehensive-guide-to-pcb-conveyor-width-adjustment\/\">https:\/\/www.chuxin-smt.com\/sl\/slug-a-comprehensive-guide-to-pcb-conveyor-width-adjustment\/<\/a><\/p><\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">About the author and how to validate these numbers<\/h2>\n\n\n\n<p>This guide is written from the perspective of an SMT line integration \/ industrial engineering practitioner with 10+ years working on SMT line layout, dual\u2011lane transport, buffering, and NG\/OK routing across consumer electronics, automotive electronics, and medical device assembly environments.<\/p>\n\n\n\n<p>Validation note: Treat vendor\u2011specific timing (for example, diverter actuation\/decision overhead) as a parameter, not a constant. Before implementing a design, measure your actual lane takt distribution, buffer occupancy behavior, merge micro\u2011stoppages, and NG routing latency in production (or during a pilot) and then re\u2011run the calculations with your site data.<\/p>\n\n\n\n<hr class=\"wp-block-separator\" \/>\n\n\n\n<p>Next steps<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><p>Adapt the worked example to your board size and UPH target, then run a short pilot: verify speed setpoints, confirm buffer slot counts, and instrument Hermes\/CFX events to validate routing timing before full rollout.<\/p><\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p>Comprehensive ultimate guide to PCB conveyor system design for dual\u2011lane high\u2011speed SMT lines \u2014 formulas, worked examples, Hermes\/CFX traceability, and buffer sizing. Read now.<\/p>","protected":false},"author":3,"featured_media":4184,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}}},"categories":[53,1],"tags":[82,58],"class_list":["post-4185","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-enterprise-information","category-company-news","tag-automatic-transposition-conveyor","tag-pcb-conveyors"],"acf":[],"_links":{"self":[{"href":"https:\/\/www.chuxin-smt.com\/es\/wp-json\/wp\/v2\/posts\/4185","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.chuxin-smt.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.chuxin-smt.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.chuxin-smt.com\/es\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/www.chuxin-smt.com\/es\/wp-json\/wp\/v2\/comments?post=4185"}],"version-history":[{"count":0,"href":"https:\/\/www.chuxin-smt.com\/es\/wp-json\/wp\/v2\/posts\/4185\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.chuxin-smt.com\/es\/wp-json\/wp\/v2\/media\/4184"}],"wp:attachment":[{"href":"https:\/\/www.chuxin-smt.com\/es\/wp-json\/wp\/v2\/media?parent=4185"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.chuxin-smt.com\/es\/wp-json\/wp\/v2\/categories?post=4185"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.chuxin-smt.com\/es\/wp-json\/wp\/v2\/tags?post=4185"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}